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Lesson 4: My Moore’s life: to be Moore, or not to be Moore?

During my forty-year career in the semiconductor industry, I have twice ridden the waves of Moore’s Law and twice left to develop non-Moore’s Law technologies. When I was an employee of IBM from 1982 to 1984, I entered into the wave of Moore’s law and participated in the development of the 1st generation CMOS (1.0 µm) and 2nd generation CMOS (0.8 µm) processes. Then, predicting that lithography technology would reach the physical limits of light wavelength resolutions at 0.1-0.2 µm, I decided to leave the wave of Moore’s Law and joined AT&T Bell Labs in order to develop multi-chip modules based on silicon substrate technology as an alternative approach to miniaturizing the integration of the ever-increasing number of transistors. Between 1984 and 1988, AT&T Bell Labs invested about 300 million dollars in recruiting hundreds of interdisciplinary (system and chip) talents to develop multi-chip modules (MCM). Sadly, it was 30 years too early. Today, TSMC’s CoWoS (chip-on-wafer-on-substrate) is similar to AT&T Bell Labs’ MCM technology from back then. The investment AT&T Bell Labs had made in MCM technology development over 30 years ago and their development of electroplating technology for copper metal interconnections on silicon wafers paved the way for R&D on electroplating process technologies for semiconductor silicon wafers.

From 1990 to 1995, my career turned back towards following the rules of Moore’s Law as I led the R&D team at TSMC to develop eight sub-generations of technology processes between 0.8 and 0.35 µm. However, I once again departed from Moore’s Law between 1999 and 2011 when I established two companies—Megic and Megica—to promote our proprietary MeGic technology. The term “MeGic” combined the words “memory” and “logic” into one word. In Chinese, the character “米 (Me)” means rice, representing the idea of a memory chip being a commodity like rice, and the character “輯 (Gic)” represents the logic chip. MeGic technology connected memory chips and logic chips face to face to increase the number of transistors and, thus, computing speed. It was a pity that this technology was also ahead of its time and did not succeed during the time. However, later in 2016, both TSMC and Intel started developing technologies that mimicked MeGic’s technology by connecting memory chips and logic chips face to face.

It is worth mentioning that the world’s largest smart phone telecommunication chip company purchased Megica in 2009 because one of the world’s largest computer CPU chip company had used Megic’s FREEWAY technology in 2007. In keeping with the rules of Moore’s law, metal interconnections on chips became narrower and narrower, increasing the density of metal interconnections connecting all the transistors on a chip. Unfortunately, this increased the resistance and capacitance of the circuits and reduced their speed. Imagine the transportation system of an urban metropolis like Taipei City, having dense and narrow roads leading to every spot of the city. However, the roads are crowded with cars and have many traffic lights, slowing speed of travel. At the time, I thought, “why not apply the 5 µm-thick electroplated copper technology we had previously developed at AT&T Bell Labs over the top-most protection layer of the chips (known as the Passivation layer)?” This became the very FREEWAY technology promoted by Megic. The 5 µm metal interconnection FREEWAY technology provided chips with high connecting speed, just like using an actual freeway for long distance travel. The metal interconnections of FREEWAY technology became thicker and wider—in a way, you could say that it moved in reverse of Moore’s Law. The Megic FREEWAY provided a new structure, a FREEWAY Architecture, for chip design. Megic registered the trademark FREEWAY in both U.S and Taiwan at the time. In July 2009, after signing and completing the contract of selling Megica to the purchasing smart phone telecommunication chip company, I was overwhelmed with excitement and felt as though Taiwan had just armed the U.S. with an incredible weapon in the race towards technological advancement.

How did I choose, after decades of riding the ebbs and flows of life in the world of semiconductors, to finally be Moore’s or non-Moore’s? The truth of the matter is that the aforementioned Logic Drive that I first proposed in 2016 is actually a fusion of both Moore’s law and non-Moore’s law approaches. The Logic Drive utilizes the power of Moore’s Law by using standard commodity FPGA chips or chiplets fabricated in a technology more advanced than 10 nm that contain a sufficient number of transistors and provide fast processing speed with low power consumption. However, the Logic Drive also leverages non-Moore’s Law concepts by packaging a multitude of standard commodity FPGA chips into an advanced multi-chip package, in which the number of transistors would be greatly increased. Interestingly enough, the current development of multichip packaging technology (the non-Moore’s Law technology) would appear to be starting its very own miniaturization journey following a scaling process much like the Moore’s law in the IC chip: the number of transistors within an area or volume of the multi-chip package will be increased yearly.

(This article was translated from the article (in Chinese) published in “DIGITIMES” on November 18^th, 2021, while with some revisions.)

Link of “DIGITIMES”: Lesson 4