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Glass Panel with embedded TGV Connectors

Multi-Chip Packaging Based on Glass Panel Fabrication Process

A thick glass substrate incorporating iCometrue’s invented Through-Glass-Via (TGV) Connector effectively overcomes the limitations of existing advanced multi-chip packaging approaches, of which each faces significant challenges in scalability, cost, and mechanical reliability:

Silicon interposer: While offering excellent electrical performance, silicon interposers are expensive—particularly for large packages. For example, the current Nvidia’s B300 GPU multichip package chip needs an interposer with a size approximately 10 cm × 10 cm; a single 12-inch wafer can only yield two to four interposers for the Nvidia’s B300 GPU multichip package, severely limiting cost efficiency and production throughput.

Fan-out-on-molding-compound with embedded silicon bridge (FOMIB): This approach provides very high-density interconnection only in limited areas of the silicon bridges, which meets the high bit-width demand between the Nvidia B300 GPU chip and the HBM module. The silicon bridges are then embedded in the molding compound. The FOMIB suffers from warpage and mechanical instability due to the low Young’s modulus of the molding compound (10–20 GPa) and its large coefficient of thermal expansion (16–22 ppm/°C) compared with silicon (2.6–3.3 ppm/°C). These mismatches degrade yield and long-term reliability.

Wafer-level multi-chip module (WMCM): In this approach a fan-out Re-Distribution Layers (RDL) interconnection scheme is formed first, the semiconductor IC chips are flip-chip bonded to the RDL interconnection scheme, which is named as “chip-last RDL package”. This approach locks capability for providing very high-density interconnection, but offers possibility of panel-level fabrication process, therefore reducing fabrication cost. Without a supporting substrate or molding compound, WMCM structures rely solely on redistribution layers, which become increasingly prone to warpage and mechanical deformation as package size grows.

PCB or BGA substrate: This approach tries to advance further for the finer metal line pitches in the current PCB or BGA substrate fabrication tools and technologies. It still locks capability for providing very high-density interconnection but offers panel-level fabrication process, therefore reducing fabrication cost. Such organic substrates exhibit low stiffness (Young’s modulus 20–24 GPa) and significant CTE mismatch (17–20 ppm/°C vs. silicon 2.6–3.3 ppm/°C), resulting in warpage and reduced structural reliability, particularly for large-area packages.

People in multichip packaging industry have been dreaming about using glass panel to replace silicon wafer for the fine-line interconnection interposer for a long time. Young’s modulus of glass is 70 –100 GPa, which is, though, lower than that of silicon (130–190 GPa), but is much higher than those of molding compound (10–20 GPa) and organic substrate (20–24 GPa). The relationships between warpage, stress, and material properties are illustrated below:

The curvature of the warpage is reversely proportional to the Young’s modulus (E_s) and the square of the thickness (t_s) of the substrate.

Silicon crystal is a God-given material, which is an element in the Group IVA of the periodic table and has a diamond cubic lattice structure. Silicon crystal offers very high stiffness (Young’s modulus 130-190 GPa), only next to the stiffness of diamond (carbon crystal). The mechanical property, in addition to the electrical properties, of the silicon crystal provide humans with the opportunity to build Artificial Intelligence. The strength and rigidity of the silicon crystal offer possibility in forming through-silicon-vias (TSVs) with small sizes (as small as tens of nanometers); TSV is an essential element in the advanced multichip packages.

Glass is not a crystalline solid but an amorphous solid. Without the strength and rigidity of the silicon crystal, it is difficult to form small through-glass-vias (TGVs) without micro-cracks. People in multichip packaging industry have been working very hard to develop TGV technology for a long time. To solve the TGV problem, iCometrue’s has an out-of-box invention in forming TGVs in the glass panel. iCometrue’s solution comprises two stages: (A) forming TGV connectors, and (B) forming big holes in a glass panel, and then embedding the preformed TGV connectors in the big holes. Worthwhile to note is that, in our invention, the silicon bridges and decoupling capacitors formed in deep trench of silicon substrates can be also embedded in the big holes of glass panel.

TGV Connector

TGV connector is iCometrue’s out-of-box invention which has not followed conventional logic thinking of forming TGVs by forming holes vertically in a glass substrate and filling the holes with metal. Instead, we form TGVs by first forming metal lines in a horizontal plane, cutting meal lines into segments, then rotating segments of metal lines 90 degrees for use as TGVs.

Refer to Fig. 1 and Fig. 2, the TGV Connector is fabricated by process steps of: (A) using mature technologies of fabricating conventional interconnection scheme on a silicon wafer or a glass wafer or panel. The interconnection scheme on the silicon or glass substrate comprises multiple metal layers each having many metal lines running in parallel with each other at a x-y horizontal plane. The interconnection scheme is formed by planar processes including laminating insulating dielectric films and copper foils, and pattering copper foils to form metal lines in the x-y horizontal plane. This approach not only ensures precision and uniformity but also enhances cost efficiency by leveraging equipment and techniques commonly used in silicon wafer, PCB panel and LCD display manufacturing facilities; (B) attaching a top silicon (or top glass) wafer or panel on the interconnection scheme; (C) cutting the parallel metal lines into segments; (D) rotating the segments by 90 degrees to obtain the TGV connector. After rotating 90 degrees, the “horizontally parallel metal lines” now are ready for use as “vertically parallel through-glass-vias”. This is an out-of-box invention! It avoids the micro-crack problem by forming small sized TGVs in the soft insulating dielectric films. Furthermore, TGV Connectors provide vertical-through-vias with dimensions as small as 5 µm in glass panel, as compared with the typical 70 – 120 µm via size achieved by existing TGV processes when glass panel is thicker than 0.5 mm.

Fig. 1 shows the process flow for fabricating of TGV Connectors.

Fig. 2 shows the schematic drawings of the TGV Connector.

Fabrication of Glass Core with Embedded TGV Connectors

The next important stage of our invention is to form big holes in the glass panel and embedding the innovated TGV connectors in the big holes of the glass panel for use as vertical through vias in the glass panel. Forming small TGVs in the glass panel is difficult, yet, forming big holes in the glass panel with size greater than 250 µm or even in mm range, as required in our invention, is easy.

After embedding TGV connectors in the glass panel, a glass core in the panel format is formed.

Fig. 3 shows the process flow for fabricating the glass core with embedded TGV Connectors.

This innovative approach removes the necessity for both laser drilling and metal filling processes, which are among the most cost-intensive and technically challenging steps in existing TGV fabrication. By employing a fully panel-level process, the overall manufacturing sequence becomes simpler, more scalable, and economically viable.

Applications of the Glass Core

There are varieties of possible applications of the glass core. Below we show examples of two applications of the glass core: (A) Glass Interposer to replace silicon interposer, and (B) PCB Glass Core to replace current PCB fiberglass-epoxy core.

(A) Glass Interposer

To replace silicon interposer, the Glass Interposer requires: (i) in addition to the TGV Connectors, further embedding silicon interconnection bridges and/or passive devices, for example, decoupling capacitors in deep trenches in a silicon substrate; (ii) forming frontside and backside Re-Distribution Layers (RDL) interconnection schemes on the top and bottom of the glass core, respectively. The frontside and backside RDL interconnection schemes are formed by forming each of RDL metal layers using sputtering adhesion metal layer and photoresist-defined electroplating copper layer, and forming each of intermetal dielectric layers using liquid (or dry film) photo-sensitive polyimide layer.

Just like the silicon interposer, the Glass Interposer provides high density interconnection between semiconductor IC chips to be flip-chip bonded to the Glass Interposer, through the embedded silicon interconnection bridges. The current AI solution using Nvidia B300 GPU chips and HBM modules causes the problem of “Tyranny of number”: the number of metal interconnects between the Nvidia B300 GPU chip and the HBM module is about 8912, which presents big challenge of interconnection schemes in the multichip packages. The embedded silicon interconnection bridges seem to offer an acceptable solution to solve “Tyranny of number” problem. Furthermore, the Nvidia B300 GPU chip consumes over 1,000 watts electricity, the embedded decoupling capacitors would provide electricity locally to reduce power/ground noises, hence reducing the power consumption. Furthermore, the Nvidia B300 GPU chip generates lots of heat, the glass substrate helps the heat spreading and conduction; further, its rigidity and stiffness helps reducing mechanical problems caused by thermal expansion.

Fig. 4 shows a Glass Interposer with CPU, GPU, SOC, and ASIC chips and HBM modules flip-chip bonded to the Glass Interposer. The embedded silicon bridge provides high density interconnection between the GPU chip and HBM module, and the passive device of the decoupling capacitor provides local power/ground source for the power-hungry GPU chip.

The Glass Interposer offers significant advantages over conventional silicon interposers or molded substrates with embedded silicon bridges as discussed above. The Glass Interposer provides a better choice for high-performance, thermally stable packaging architectures, particularly suited for HPC (high-performance computing) and AI applications.

(B) PCB Glass Core to replace current PCB fiberglass-epoxy Core

This application is just straightforwardly using the glass core with embedded TGV connectors to replace the current PCB fiberglass-epoxy (for example, FR4) core. The rest of the processes and features are the same as the current advanced multichip packages using PCB substrates, particularly the fine-line BGA substrates. In the PCB Glass Core, the glass substrate serves as the central core, in which TGV Connectors, and optionally silicon bridges or passive elements, are embedded. standard PCB fabrication processes are then applied to build metal interconnections, dielectric layers, and contact pads on both surfaces.

The process in this application includes forming the frontside and backside interconnection schemes on the top and bottom of glass core with embedded TGV connectors using standard PCB fabrication processes including: (A) modified semi-additive process (MSAP) using BT dry films and copper foils, and/or (B) semi-additive process (SAP) using ABF dry films and electroless plated seed layers. The modified semi-additive process includes process steps of: (A_i) laminating copper foils and BT dry films with the glass core, (A_ii) forming openings for blind vias in copper foil and BT dry film, (A_iii) forming copper seed layer by performing electroless copper plating, (A_iv) forming and patterning photoresist layer, (Av) performing copper electroplating, (A_vi) stripping the remained photoresist, and (A_vii) removing the unwanted copper foils and seed layers. The semi-additive process includes process steps of: (B_i) laminating ABF dry films with the glass core, (B_ii) forming openings for blind vias in ABF dry film, (B_iii) forming copper seed layers by performing electroless copper plating, (B_iv) forming and patterning photoresist layer, (B_v) performing copper electroplating, and (B_vi) stripping the remained photoresist and removing the unwanted Cu seed layers.

Moore’s Journey: From Round Silicon Wafer to Rectangular Glass Substrate

With its high Young’s modulus and a coefficient of thermal expansion closely matched to silicon, glass demonstrates excellent mechanical and thermal properties, making it the optimal material choice for large-size, advanced multi-chip packaging.

iCometrue is pioneering a new era in advanced multichip packaging by introducing glass substrates embedded with TGV Connectors, which provides a practical and scalable alternative to existing TGV processes. This innovation further embeds silicon interconnection bridges and decoupling capacitors in the glass core, which enables super-high-density, high performance, reliable, and cost-effective multichip packages. Applying our innovation in Glass Interposers and PCB Glass Cores, iCometrue is establishing the foundation for the next generation of multichip integration, extending Moore’s Law into the era of glass-based system packaging and accelerating the development of high-performance computing and AI applications.